Yes, I'm typically the high-priest of "let him do what he wants" and this seems to be a contradiction.

What the O/P indicated he wanted to do was to integrate what he felt was a proven HDL core of a CAN conroller with the T51 core, presumably the one on OPENCORES.ORG.

However, since the O/P didn't seem to realize that the architecture is vastly different from the other MCU's together with which the CAN controller core he wished to use had been "proven" and since he clearly indicated he had no idea of how to set the ext_ram_en signal in the core, he clearly didn't understand how the instruction set works within that core.

It was apparent that he and his colleagues hadn't considered the effect of using external memory mapping rather than SFR-mapping for their controller. First of all, it becomes a multi-instruction sequence changing any control bits in the peripheral.

While it's not difficult to do things either way, the O/P should have considered the effect of his mapping choice, and, of course, should have considered how the mapping was to be accomplished. HDL's while looking like HLL's do not "take care of the low-level details" in the same way as one might conclude 'C' or Pascal might do that.

My exhortation to "back away and rethink" the decision to map into external memory space, taken in the context of the O/P's apparent lack of awareness of the consequences, was simply intended to wake the O/P up to the details of his apparently flippant decision to do that. Apparently he and his colleagues hadn't yet considered where the "ext_ram_en" signal orginates.

RE