I'm somewhat persuaded that the approach the Christian Meier and his colleagues are taking has not been sufficiently thought-out.

You're right in that I've been poking at them in the hope of stimulating new thought. They should consider why it is that on-chip resources are interfaced via the SFR space. They should consider why it is that resources on the chip are seldom provided with external-memory-mapped interface.

I'm hoping they'll back away and take another look at it.

I suspect they'll have very little trouble integrating their CAN controller with the T51 core, once they understand the workings of the 805x architecture and its implementation in FPGA.

RE