Isn't the T51 core a one-clocker? I haven't looked at it in quite a while, and have looked at quite a number of others as well.

Implemented in Spartan-3E, it should be possible, not only to make the single-cycle instructions execute in one oscillator cycle, but should, in fact, be able to execute pretty much any instruction, aside, perhaps, from read-modify-write types, in one cycle. Further, some instructions can be executed concurrently or even out of order, if you're inclined to fiddle with the logic. One could, I suppose, depending on the FPGA family, even make read-modify-write instructions single-clock operations. The associated penalty in either performance or resource requirements would be determined on the basis of a tradeoff.

In FPGA, it's quite up to you whether the "view" into code memory is 4 bits wide or 128, so you can pick and choose which instructions you execute and when you do so.

Using SFR-space is as much a philosophical advantage as anything else. I/O occurs through SFR's. There's no compelling reason to change that if you're "rolling-your-own" MCU in FPGA. Esternally mapped peripherals enjoy no advantage over internally mapped ones. All you have to do is to provide the data paths and logic to implement your peripheral hardware such that its controls and registers live, i.e. are addressable, in SFR space in order to make them "built-ins."

RE