Hi Grant,

if you measure the static current consumption of a simple standard CMOS inverter with typical push pull output you will find something interesting: The current consumption is only very little if the input voltage is exactly at the rails, or by other words at 0V or Vcc of the CMOS inverter. This has to do with the fact, that the CMOS inverter contains a NMOSFET and a PMOSFET which become both partially turned on when the input voltage is anywhere between the rails. Of course, then the current consumption will dramatically rise.

If you take a look into the datasheet of a CMOS RAM which is specified for data retention, you will find that the little current consumption is only valid if the input voltages are no more than 0.2V away from the rails, or by other words either <0.2V or >Vcc-0.2V. This has to be taken into account when designing a CMOS RAM circuit for data retention. If you violate this specification during power down of rest circuitry your coin will discharge very rapidely!

But why should the power down of rest circuitry be a problem for the CMOS RAM? Because the inputs of the CMOS RAM suffer from input leakage currents. (This is true for all digital circuitry. Every gate suffers from input leakage current.) A typical maximum rating of input leakage current of a CMOS RAM for data retention is +/-1 microampere. Now you must provide a current path for all the input leakage currents of CMOS RAM down to 0V. And the voltage drop across this path must not rise over 0.2V!

The simplest idea is to have pull-down resistors at each input of CMOS RAM of < 0.2V / 1 microampere = 200k. I remember circuits with lots of 150k arrays hanging at the address and data lines of CMOS RAM for this purpose. These rather high ohmic pull downs wouldn't even conflict with the lower ohmic pull-ups 80C51 circuits sometimes need at the port pins. You know that the 80C51 sometimes toggles the port lines high with a strong internal pull-up only for two oscillator periods. Afterwards only a weak internal pull-up provides the "1" at output. The /WR and /RD lines are affected by this performance, e.g.. To prevent that noise can ruin the output signal of port line a pull-up of about 10k is usually added.

The method with the pull-downs works very well, usually. But it has its limitation if you want to parallel many of the CMOS RAMs, because adding CMOS RAMs would also increase the input leakage currents. For n CMOS RAMs the power down resistor at each shared line must be decreased by a factor of n.

Another method is to use pull-ups as current path for the input leakage currents of CMOS RAM. As I mentioned above many 80C51 applications and others have already pull-ups of about 4k7...22k sitting at the address, data and control lines. If your power supply is designed in such a way that Vcc goes down to 0V when the circuit is powered down, you can use the method with the pull-ups. Sometimes it makes sense to add a pull-down in the kOhm range from the Vcc rail to 0V, to guarantee that the input leakage currents can flow unhinderedly to 0V. An example: If you have one CMOS RAM with 26 address, data and control lines, with 10k pull-ups at each line, then across each pull-up a voltage of < 1 microampere x 10k = 0.01V will drop when powered down. And with an additional 4k7 pull-down from the Vcc rail to 0V an additional voltage drop of < 26 microampere x 4k7 = 0.12V will occur. With these values you would stay within the specifications and the current consumption of CMOS RAM would be very low. The coin powered data retention would work as expected.

Kai