Thanks Richard. I will look into some of the things you mentioned. I'm sure my original post lacked clarity. This is an old school expanded bus system with standard 6264 type SRAM that is non-volatile via a small coin cell battery. The only thing I can do is remove the (socketed) SRAM to install a larger SRAM (board) that will be banked in at the existing memory map. The banks will be controlled by physical SPST or SPDT type switches. That's the whole scope.

So my concern was with the address line connected to the bank select switch. When the unit is powered off, almost everything is powered down except for the SRAM and a small amount of CMOS logic connected to it (for reset management etc making sure there are no spurious writes during power on/off). Really it's just what to do with the high order address-line also known as bank-select.