This is how I read it:

Interrupt interrupting main:
12 cycles until first instruction of ISR

Interrupt interrupting a lower-priority ISR while the ISR is running:
12 cycles until first instruction of higher-priority ISR

Interrupt interrupting a lower-priority ISR while CPU is entering that ISR:
<= 12 cycles due to late-arriving feature (so don't count on there being a minimum latency of more than one cycle)

Lower-priority interrupt going pending during higher-priority ISR:
6 cycles after higher higher-priority ISR finishes due to tail-chaining feature


Of course, the above does not take things into account like additional latencies incurred by explicitly disabling/enabling interrupts.