| ??? 04/21/11 16:57 Read: times |
#181968 - Cortex NVIC behavior. Responding to: ???'s previous message |
Erik Malund said:
the way I read the documents, what you say is true IF the higher priority interrupted the lower priority, but not if "lower priority interrupt going pending during the higher priority interrupt" If a lower priority interrupt goes pending during a higher priority interrupt, the execution of the lower priority interrupt starts 6 cycles after the last instruction of the higher priority ISR due to the tail-chaining feature. interrupt 1 getting out 6 clocks interrupt 2 getting in 12 clocks, no mention if any pf the nmain get done in-between This is what the tail-chaining feature prevents. It's ISR_1 (6 cycles for tail-chaining) ISR_2, with no cycles for the main program in between. This is different from ARM7 where main would always get at least one cycle once an ISR returns. However, be aware the the interrupt latency isn't constant. It can actually be less than 12 cycles if a higher priority interrupt becomes pending during the 12 cycles it takes to enter a lower priority interrupt. The CPU recognizes "late-arriving" higher priority interrupts and can enter their ISR instead of the original lower priority ISR. |
