??? 04/20/11 14:12 Modified: 04/20/11 14:44 Read: times |
#181957 - a caveat Responding to: ???'s previous message |
And when using a small ARM, you normally have access to a number of big-brothers that are code compatible (including peripherials) but has one or more of:
- more pins - more peripherials - more memory - faster core - ... and higher interrupt latency I, actually, just did a thing with a 72MHz ARM where I wished it had been a f120. for the Cortex (the ARM in question) an interrupt interrupting an interrupt has a latency of min. 18 clocks! an equal or lower priority interrupt going pending when another ISR is executing is even worse (maybe just as bad, the docs are a bit fuzzy on this one) Erik reference http://infocenter.arm.com/help/topi...p1_trm.pdf |