an equal or lower priority interrupt going pending when another ISR is executing is even worse (maybe just as bad, the docs are a bit fuzzy on this one)

In that case, the lower priority ISR starts 6 cycles after the higher priority ISR finishes due to the tail-chaining feature (i.e. the CPU moves directly to the next ISR instead of doing a regular ISR exit and then a regular ISR entry).
the way I read the documents, what you say is true IF the higher priority interrupted the lower priority, but not if "lower priority interrupt going pending during the higher priority interrupt"

Erik Malund said:for the Cortex (the ARM in question) an interrupt interrupting an interrupt has a latency of min. 18 clocks!

Where in the docs can I find this? The regular ISR entry latency is 12 clocks, and I don't believe this changes if a higher priority interrupt preempts a lower priority interrupt.
interrupt 1 getting out 6 clocks interrupt 2 getting in 12 clocks, no mention if any pf the nmain get done in-between

anyhow
However, due to all of the automatic register pushes happening during ISR entry, if you need ultra-low ISR latencies, the Cortex-M3 (and similar) architecture isn't the right thing for the job.

was the point I tried to make.

I got in the, for many, well known situation: "program this board to do so".

Erik