HI All,

I am hoping some can help me interpret the I2c bus specification for one parameter.

Background
==========
The I2c specification show a SDA/SCL slope control - fall time for 400KHz speed (Fast Mode) as 20nS + Cb*0.1 [ where Cb is bus capacitance]

But yet there is NO slope control all speed for standard (100KHz) and Fast Mode Plus (1MHz).

Please refer to NXP(Philips) I2C Specification manual.
www.nxp.com/acrobat_download/usermanuals/UM10204_3.pdf

See
a) Page 36 table 5 tof output fall time from VIHmax to
VILmax

b) Page 37 table 6 tf fall time of both SDA and SCL signals

Questions
==========
What is the intention for this parameter? it's on the 400kHz bus speed requirement but not on the 100kHz, 1MHz requirement.

What is the effect if the I2c master has faster fall time?
(IE FET open drain driving the bus).

Thanks in Advance.
Joe