| ??? 12/05/07 03:47 Read: times |
#147889 - Application specific Responding to: ???'s previous message |
Dear Kai et al,
Thank you for your answers. Kai Klass said:
Everything between can be seen and can be useful. It always depends! Missed to type the value, Kai?! The decoupling element shouldn't be greater than 0805, otherwise package inductance can be too high. Avoid paralleling. And, the most important of course, use a solid ground plane. Yes, understood. 0603 are quite good in ESL. LRC-filter for each chip (even the digital ones) consisting of a soft ferrite bead in 0603 package (about 1µH effective inductance), a 4R7 minimelf SMD-resistor and a 10µF/10V/X5S ceramic high cap in 0805 package. This gives me a better answer: 10uF ceramic! If you ask me, then don't use small capacitances. The smaller this capacitance, the higher the resonance frequency in combination with Vcc trace inductances and the lower the dampening of these resonances. Take at least 100nF for each chip. Increase the capacitance if you like, but don't lower it. Sufficient! Thanks, Vignesh |
| Topic | Author | Date |
| 1uF or 0.1uF or 0.01uF for decoupling? | 01/01/70 00:00 | |
| Resonance on supply lines | 01/01/70 00:00 | |
| laziness? problems? | 01/01/70 00:00 | |
| Contamination | 01/01/70 00:00 | |
| Exactly | 01/01/70 00:00 | |
| In the FAQs | 01/01/70 00:00 | |
| This depends on your application | 01/01/70 00:00 | |
| Application specific | 01/01/70 00:00 | |
| Values | 01/01/70 00:00 | |
| Does this applies equally to | 01/01/70 00:00 | |
| This also depends | 01/01/70 00:00 | |
This also depends | 01/01/70 00:00 | |
| Also | 01/01/70 00:00 | |
| location, location, location | 01/01/70 00:00 |