I am starting this thread to get my understandings correct regarding decoupling.

My (present)understandings about selecting a decoupling capacitor are:

1. The capacitor should have lowest possible ESL - because the inductance should not impede the high current to be supplied by the de-cap in very short duration - hence physically smaller sizes (0805, or better 0603, even better 0306) should be chosen
   
   
2. The capacitor should have lowest possible ESR - because the voltage drop due to current flowing * ESR should be minimum, also the heat produced by ESR * Current * Current
   
   
3. Value of the capacitor - depends upon how much dynamic current will flow during the clock edges or logic state change into the Vcc pin of the IC, and there should be enough charge in the capacitor such that the voltage across the capacitor should not drop. For instance, an 8051 running at 12MHz, will have clock edges at every 42ns. Assuming that the rise/fall time of the every clock edge being 10% of 42ns = 4.2ns. Assuming that the 8051 IC needs 100mA of dynamic current at every clock edge, so the decoupling capacitor should provide this 100mA for 4.2ns without the voltage dropping by 0.5V, then
   
   I * t = C * V
   100mA * 4.2ns = C * 0.5V
   or C = (100mA * 4.2ns) / 0.5 = 820pF
   

The part which I intend to use is: ECJ-1VB1C105K, which is a 1uF, 6.3V, 10% tolerance, 0603, X7R Multi Layer Ceramic(MLC) capacitor from Panasonic. In my application, I should decouple 89S51 in TQFP-44 package, running at 4V.

My questions are:

1. The calculations above says a value of 820pF, and assuming variation over temperature, and initial tolerance all included to a value of 2nF, is there any advantage by using a higher value of capacitance?
   
2. Given that for a 0603 package, the ESL does not vary with capacitance value, and for a Multi Layer Ceramic dielectric, the ESR does not vary much with capacitance value, then is 1uF better than 0.1uF?
   
3. The impedance graphs of the capacitor are taken from Panasonic website, which states that the
   
   
   • ESL is less than 2nH in the 1MHz to 100MHz range. So voltage drop due to inductance is
     V = -L di/dt
     = -2n (100mA/4.2n) = approx -50mV
     
   • ESR is less than 10 milliOhms in 1MHz to 100MHz range
     
   • Impedance of the capacitor is less than 500 milliOhms in 1MHz to 40MHz range, so the drop for a 100mA of current is 50mV
     
   Is 1MHz to 40MHz range what I should be looking at?
   
4. I cannot find similar impedance graph for a capacitor from same series but with different capacitance, so I am not able to compare. How better / worse will a [100nF/10nF/1nF] /0603/X7R MLC capacitor be?
   

Thanks for your time,
Regards,
Vignesh