The 8x300 used a Harvard Architecture with simple load and store instructions. The only "gotcha", IIRC, and it has been 30 years or so, was that each instruction, while it took only 300 ns to execute each of its 8 instructions, was a load and store, with logic operations and shifts in nearly every instruction. Each instruction had a data source and data destination outside the CPU. The version that I used had already been sped-up to 250 ns per cycle.

It is, in fact, a "Cambrian" DSP, perhaps "pre-Cambrian," but it was the first common RISC that I ever encountered. The technology was, indeed, bipolar, but not TTL, as it was current-mode-logic, like ECL, but TTL-compatible, intgrated injection logic (IIL) requiring an external current pump.

RE