If i recall correctly, the basic tenets of RISC were
load/store architecture
single cycle execution
large register array

The idea was to simplify the instruction decoder so that you could execute the instruction in the smallest number of clocks thus improving performance. It used to be the case where you'd try to get the most performance from the least logic, but since you can pack an awful amount of logic onto a chip these days, you can have large pipelines and more logic to parallelize the instruction decode and execution thus increasing performance.