I am constrained to design 8051s that are drop-in replacements for existing chips. So if I make a better reset, it still has to work in old applications.

In an effort to determine how much I can get away with before I start to affect existing applications, I would like to pose the following questions:

1. I can put an N-bit (4096?) counter on the oscillator to insure that it has started and stabilized before I release internal reset. That would potentially delay system startup by a few milliseconds. Is that a problem? Do you expect the processor to start executing immediately after reset is removed?

2. I can put a voltage detector that will force a hard reset at Vdd = 4.25 (or whatever). On the downside, this might force the processor into reset under noisy conditions (such as whenever the motor turns on) (or worse, whenever the flash is programmed!). To compensate, I could require the detector to have a low voltage signal for 3 (or N) clocks before activating reset. Still, would anyone here authorize a second source for an existing design with that level of reset change? Do you trust your older systems to have a clean supply?

3. I can make a configuration bit set the polarity of the reset pin. I suppose that the bit should also change the pulldown resistor into a pullup resistor. That would mainly be for new designs (I can always hope). So would you use an active low reset if it was available?