| ??? 03/01/07 07:19 Read: times |
#133995 - Why do you need to do that? Responding to: ???'s previous message |
The CPLD doesn't have to be reprogrammed every power cycle as would an FPGA. It has non-volatile program memory. Once programmed, it stays that way until it's reprogrammed.
As Sasha Jevtic has said, there are ways, of course. I'm always curious why someone would want to do this sort of thing, though. Please explain. RE |
| Topic | Author | Date |
| "Programming CPLD with AT89S52" | 01/01/70 00:00 | |
| Things of the sort can be done... | 01/01/70 00:00 | |
| Why do you need to do that? | 01/01/70 00:00 | |
| Maybe... | 01/01/70 00:00 | |
| absolutely! But I'm still curious ... | 01/01/70 00:00 | |
| Why not? | 01/01/70 00:00 | |
| Altera used to have some code available | 01/01/70 00:00 | |
| jam vs. svf | 01/01/70 00:00 | |
| Programming CPLD with AT89S52 | 01/01/70 00:00 | |
| like I said.. | 01/01/70 00:00 | |
| Programming CPLD with MCS-51 | 01/01/70 00:00 | |
| forget JAM | 01/01/70 00:00 | |
| at 8Kbyte AT89S52 | 01/01/70 00:00 | |
| Understanding the problem | 01/01/70 00:00 | |
| it's relative | 01/01/70 00:00 | |
| Cypress CPLD=Xilinx CPLD | 01/01/70 00:00 | |
| You mean CY7C256? | 01/01/70 00:00 | |
| CY27256P160 | 01/01/70 00:00 | |
| Cypress doesn't know what that is | 01/01/70 00:00 | |
| sorry about the double-post | 01/01/70 00:00 | |
| Yes CY7C256 TQFP | 01/01/70 00:00 | |
Pin assigment at CPLD and AT89S52 | 01/01/70 00:00 |