Well I don't think it's the optimal way to use exactly the 4004 architecture for a softcore, although it was certainly a nice mental excercise. IMHO a simpler 8-bitter might make better use of the available resources for similar performance - but that's just my guess, I have zero experience.

One thing worth noting - the design of 4004 is optimalized down to transistor level - this is nothing like a "standard cell" approach, this is much more "analog" design - plus dynamic memory cells for registers and similar stuff. Note the different gate width for each transistor at the original schematics. This was the only way how to achieve the ultralow transistor count (~2000) and die size. I'd like to know now much of FPGA resources (and perhaps an estimate how does it convert to transistor count)...

Jan Waclawek

PS. Do you have KBD and DAA in your implementation? :-)