| ??? 10/05/12 19:45 Read: times |
#188584 - You don't have to do that Responding to: ???'s previous message |
External memory interfaces to 805x's are, for the most part, quite generic.
It wouldn't be hard for you to provide a schematic that's similar but not identical to the circuit with which you're having problems. Just include enough of the circuitry to show the external memory interface and all the circuitry that might be causing your timing issues. Once we see that, someone's likely to recognize your problem from one he/she's had before. You don't have to compromise any trade secrets, not that it's likely to happen. Without that, it's unlikely any progress will be made. RE |
| Topic | Author | Date |
| SRAM issues | 01/01/70 00:00 | |
| Setup and hold times? | 01/01/70 00:00 | |
| RAM issues | 01/01/70 00:00 | |
| Or narrow pulses ? | 01/01/70 00:00 | |
| Address setup time | 01/01/70 00:00 | |
| did you change the arbitration? | 01/01/70 00:00 | |
| Ram issues | 01/01/70 00:00 | |
| P0, P2 for memory only, or ... | 01/01/70 00:00 | |
| p0 and p2 | 01/01/70 00:00 | |
| If you latch both P0 and P2, there will be stabile A15-A0 | 01/01/70 00:00 | |
| Arbitration circuit | 01/01/70 00:00 | |
| It's a bit tricky synchronizing an 805x with 68k series | 01/01/70 00:00 | |
| you are using a latch, and not a flipflop, right? | 01/01/70 00:00 | |
| FF or latch | 01/01/70 00:00 | |
| It's a mistake I've seen a time or two ... | 01/01/70 00:00 | |
| time wasting | 01/01/70 00:00 | |
| no circuit diagram | 01/01/70 00:00 | |
You don't have to do that | 01/01/70 00:00 |