| ??? 09/26/12 12:13 Read: times |
#188460 - RAM issues Responding to: ???'s previous message |
We did notice that it seems to have problem with the lowest 8 address bit which is multiplexed for 8051. The 8051 write to a wrong address. The 68k side seems OK. Could the issues is with the latch circuit? |
| Topic | Author | Date |
| SRAM issues | 01/01/70 00:00 | |
| Setup and hold times? | 01/01/70 00:00 | |
| RAM issues | 01/01/70 00:00 | |
| Or narrow pulses ? | 01/01/70 00:00 | |
| Address setup time | 01/01/70 00:00 | |
| did you change the arbitration? | 01/01/70 00:00 | |
| Ram issues | 01/01/70 00:00 | |
| P0, P2 for memory only, or ... | 01/01/70 00:00 | |
| p0 and p2 | 01/01/70 00:00 | |
| If you latch both P0 and P2, there will be stabile A15-A0 | 01/01/70 00:00 | |
| Arbitration circuit | 01/01/70 00:00 | |
| It's a bit tricky synchronizing an 805x with 68k series | 01/01/70 00:00 | |
| you are using a latch, and not a flipflop, right? | 01/01/70 00:00 | |
| FF or latch | 01/01/70 00:00 | |
| It's a mistake I've seen a time or two ... | 01/01/70 00:00 | |
| time wasting | 01/01/70 00:00 | |
| no circuit diagram | 01/01/70 00:00 | |
You don't have to do that | 01/01/70 00:00 |