| ??? 09/26/12 21:51 Read: times |
#188465 - It's a bit tricky synchronizing an 805x with 68k series Responding to: ???'s previous message |
A lot depends on which68K CPU you're using. The reason is that, depending on whic 68K CPU you have, the bus cycles are quite regular and symmetrical with some while not so much with others (particularly the later ones). It's been suggested that we might be more helpful if we could look at the arbitration logic and system timing. The 68K has a signal that can be used to synchronize its operation with that of another processor, in this case the 805x, which has no such signal.
I worked with 68K CPU's when they (and the 805x) were new. I haven't fiddled with 'em since the 68030 and beyond became popular. We did all sorts of tricky things back then, including operating pairs of 'em on opposite phases of the clock, using the same shared memory, which is not so easily achieved with Intel processors. It would be interesting to see how the 805x's ALE and the 68K's DTACK signals are used. RE |
| Topic | Author | Date |
| SRAM issues | 01/01/70 00:00 | |
| Setup and hold times? | 01/01/70 00:00 | |
| RAM issues | 01/01/70 00:00 | |
| Or narrow pulses ? | 01/01/70 00:00 | |
| Address setup time | 01/01/70 00:00 | |
| did you change the arbitration? | 01/01/70 00:00 | |
| Ram issues | 01/01/70 00:00 | |
| P0, P2 for memory only, or ... | 01/01/70 00:00 | |
| p0 and p2 | 01/01/70 00:00 | |
| If you latch both P0 and P2, there will be stabile A15-A0 | 01/01/70 00:00 | |
| Arbitration circuit | 01/01/70 00:00 | |
| It's a bit tricky synchronizing an 805x with 68k series | 01/01/70 00:00 | |
| you are using a latch, and not a flipflop, right? | 01/01/70 00:00 | |
| FF or latch | 01/01/70 00:00 | |
| It's a mistake I've seen a time or two ... | 01/01/70 00:00 | |
| time wasting | 01/01/70 00:00 | |
| no circuit diagram | 01/01/70 00:00 | |
You don't have to do that | 01/01/70 00:00 |