| ??? 09/26/12 10:21 Read: times |
#188459 - Setup and hold times? Responding to: ???'s previous message |
Maybe one side have incorrect hold times. So it removes the control signals (address, r/w signal, ...) too soon. The slower memory chip continued to hold the data available a number of ns longer. With a faster RAM, you might now sometimes or always read garbage because the RAM isn't driving the data lines anymore when the processor finally do latch the data. |
| Topic | Author | Date |
| SRAM issues | 01/01/70 00:00 | |
| Setup and hold times? | 01/01/70 00:00 | |
| RAM issues | 01/01/70 00:00 | |
| Or narrow pulses ? | 01/01/70 00:00 | |
| Address setup time | 01/01/70 00:00 | |
| did you change the arbitration? | 01/01/70 00:00 | |
| Ram issues | 01/01/70 00:00 | |
| P0, P2 for memory only, or ... | 01/01/70 00:00 | |
| p0 and p2 | 01/01/70 00:00 | |
| If you latch both P0 and P2, there will be stabile A15-A0 | 01/01/70 00:00 | |
| Arbitration circuit | 01/01/70 00:00 | |
| It's a bit tricky synchronizing an 805x with 68k series | 01/01/70 00:00 | |
| you are using a latch, and not a flipflop, right? | 01/01/70 00:00 | |
| FF or latch | 01/01/70 00:00 | |
| It's a mistake I've seen a time or two ... | 01/01/70 00:00 | |
| time wasting | 01/01/70 00:00 | |
| no circuit diagram | 01/01/70 00:00 | |
You don't have to do that | 01/01/70 00:00 |