| ??? 08/13/10 19:28 Modified: 08/13/10 19:30 Read: times |
#177998 - no, it is 'random' because .. Responding to: ???'s previous message |
no, it is 'random' because unless the unlikely event of all happening simultaneously (precisely or during a (I definitely hope) brief disabling of interrupts you NEVER can know if 'A' and 'B' becones pending while 'C' executes.
Also the hopefully brief period of disabled interrupts will, most likely be overshadowed by an ISR of same or higher priority executing. Anyhow, the issue was "Has anyone ever had a reason to take the "interrupt priority list" into consideration ?" The intricacies of the interrupt mechanism should be well understood by all '51 users. It is my (unwashed) opinion that any reliance on the "interrupt priority list" would be sheer folly. If anyone can correct me with a satisfactory example, please do. Erik |
| Topic | Author | Date |
| the "interrupt priority list" | 01/01/70 00:00 | |
| latency calculation | 01/01/70 00:00 | |
| but | 01/01/70 00:00 | |
| Do I understand this correctly... | 01/01/70 00:00 | |
| priority (IP) and 'polling sequence" (the chip) | 01/01/70 00:00 | |
| how to interpret "interrupts occuring at the same time | 01/01/70 00:00 | |
| sequence can't be influenced | 01/01/70 00:00 | |
| no, it is 'random' because .. | 01/01/70 00:00 | |
latency calculation | 01/01/70 00:00 |