| ??? 08/13/10 18:01 Read: times |
#177996 - sequence can't be influenced Responding to: ???'s previous message |
Erik Malund said:
the sequence is still random Well, it is fixed in the silicon... but I presume, you meant that it cannot be influenced by the user, even if user would like to have interrupt C to be of lowest latency. That's true but still the user sometimes could choose based on this property. Say, for a low latency timer, you should prefer T0 before T1, T2 or any other. Yes this is a very niche application. In fact, authors of '51 did not mean the itnerrupt polling to be a feature anyhow useful or exploitable for the user. The polling sequence is simply a result of the design - imagine how would YOU design an interrupt controller block? - and simply the status quo is documented, take it or leave it. JW |
| Topic | Author | Date |
| the "interrupt priority list" | 01/01/70 00:00 | |
| latency calculation | 01/01/70 00:00 | |
| but | 01/01/70 00:00 | |
| Do I understand this correctly... | 01/01/70 00:00 | |
| priority (IP) and 'polling sequence" (the chip) | 01/01/70 00:00 | |
| how to interpret "interrupts occuring at the same time | 01/01/70 00:00 | |
| sequence can't be influenced | 01/01/70 00:00 | |
| no, it is 'random' because .. | 01/01/70 00:00 | |
latency calculation | 01/01/70 00:00 |