??? 08/10/10 15:38 Read: times |
#177929 - Quite related and valuble Responding to: ???'s previous message |
Erik Malund said:
Be aware that the single-clock SILabd chips, when configured as quasi, do not have the "brief heavy pullup" multi-clock chips have.
Thanks Erik. Such insights can only come from friends in forums. Raghu |
Topic | Author | Date |
Pulse degradation | 01/01/70 00:00 | |
For many purposes, slow flanks are not a problem | 01/01/70 00:00 | |
Slew-rate limiting | 01/01/70 00:00 | |
Extending SiLabs TestBoard I/O | 01/01/70 00:00 | |
Solved.. | 01/01/70 00:00 | |
piggy back PCB? | 01/01/70 00:00 | |
maybe not totally related | 01/01/70 00:00 | |
Quite related and valuble | 01/01/70 00:00 | |
Brief Heavy or Not | 01/01/70 00:00 | |
Series resistors will do the trick! | 01/01/70 00:00 | |
Pro vs Amatuers | 01/01/70 00:00 | |
I'd like to rephrase | 01/01/70 00:00 | |
Theory first, then lots of testing | 01/01/70 00:00 | |
Environment... | 01/01/70 00:00 | |
! Amused![]() | 01/01/70 00:00 |