??? 04/19/10 01:53 Read: times Msg Score: +1 +1 Good Answer/Helpful |
#175115 - Another Strong Reason... Responding to: ???'s previous message |
Another strong reason to be using a PLL in a design is that it offers, provided you have proper components selected, the ability to pick the highest possible performance when you need it for algorithm execution. But then when there is nothing to do, particularly when you are running on a battery, you can disable the PLL and run at the lowest frequency feasible. This can result in a dramatic savings of power resulting in much longer battery life and a greener product.
Michael Karas |
Topic | Author | Date |
Benefit of a higher SYSCLK ? | 01/01/70 00:00 | |
Depends | 01/01/70 00:00 | |
Use what you pay for... | 01/01/70 00:00 | |
Quite common to halt/sleep core during ADC capture | 01/01/70 00:00 | |
Seems to be a demo of various items... | 01/01/70 00:00 | |
Another Strong Reason...![]() | 01/01/70 00:00 | |
if you set it high enough ... | 01/01/70 00:00 |