Thanks for all the responses.

First to answer Per, the code does nothing more than collect the analog values, average them and send them to the serial port. And the ADC conversion needs just about 6us and a setttling time of another 10 us. Reason why a total of 20us has been allotted. And the samples are read once every 250ms ! So thats about the 'demand' on speed.

I fully agree with Mike in that the code being a sample, can demo more than just ADC reads. It shows how to use the PLL for clock multiplication; average the acquired raw values and thus improve on the resolution etc.

And yes when you clock it as fast you can, maybe you dont have to worry on resources as Erik pointed out. The point to slow down the core when ADC conversion is underway could be effective when you cross 12bit resolution ??

Thanks

raghu