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???
04/18/10 13:53
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#175109 - Quite common to halt/sleep core during ADC capture
Responding to: ???'s previous message
Yes, quite a lot of processors has notes that for optimum ADC results, the user should consider halting the processor core during the measurements. This isn't so common for processors with 8-bit ADC resolution, but when you get fast 10-bit, 12-bit or even higher-resolution ADC, the noise from the processor core can result in one or more bits of noise in the samples.

If capturing a DC level, this problem can be reduced by averaging multiple samples. But when capturing a constantly changing signal, you can't average multiple samples, so the quality of the sampled data directly follows from the amount of noise from the processor core.

List of 7 messages in thread
TopicAuthorDate
Benefit of a higher SYSCLK ?            01/01/70 00:00      
   Depends            01/01/70 00:00      
   Use what you pay for...            01/01/70 00:00      
      Quite common to halt/sleep core during ADC capture            01/01/70 00:00      
      Seems to be a demo of various items...            01/01/70 00:00      
         Another Strong Reason...            01/01/70 00:00      
   if you set it high enough ...            01/01/70 00:00      

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