Some processors/architecures supports "soft" interrupts by writing to interrupt bits, similarly to if the hardware had set them. This can sometimes be (ab)used to create critical sections that are trigged by the normal code and protected from interrupts of low or medium level, while still allowing critical high-level interrupts to be serviced. Some processors may show interrupt bits as R/W but with the little addendum that a write may only clear the bits, so you can't fake an interrupt but can "disarm" a pending interrupt for a device before enabling interrupts for it.