| ??? 03/29/10 19:43 Read: times |
#174606 - Actually very relevant Responding to: ???'s previous message |
Of course it is important - what should the processor do after leaving an interrupt, while having several new interrupts pending?
Or what the processor should do after leaving a critical section that had interrupts disabled. Having multiple interrupts pending at the same time is not an unreasonable situation if you are running SPI + timer(s) + UART (+ possibly second UART) + I2C + ... The only time you could consider it irrelevant is when the processor is not busy with interrupts, and something happens that trigs both a high- and a low-prio interrupt. In that case you could consider the priority irrelevant, since only random chance will decide if the two interrupts gets trigged on the same cycle, or if one of the events is one or more clock cycles before the other. |
| Topic | Author | Date |
| Timer Problem Assembly Code | 01/01/70 00:00 | |
| Interrupt priorities... | 01/01/70 00:00 | |
| Also... | 01/01/70 00:00 | |
| The missing words | 01/01/70 00:00 | |
| You sure? | 01/01/70 00:00 | |
| many ways to skin a cat | 01/01/70 00:00 | |
| Actually very relevant | 01/01/70 00:00 | |
| My impression is | 01/01/70 00:00 | |
| Interesting, but missing the point surely... | 01/01/70 00:00 | |
| Interrupts are 'saved' | 01/01/70 00:00 | |
| Soft interrupts | 01/01/70 00:00 | |
| in a '51 forum | 01/01/70 00:00 | |
| Still missing the point... | 01/01/70 00:00 | |
| the missing reti's have already been mentioned | 01/01/70 00:00 | |
Apart from missing reti... | 01/01/70 00:00 | |
| Interupt priorities | 01/01/70 00:00 |