| ??? 03/29/10 21:27 Read: times |
#174609 - My impression is Responding to: ???'s previous message |
Or what the processor should do after leaving a critical section that had interrupts disabled.
Having multiple interrupts pending at the same time is not an unreasonable situation if you are running SPI + timer(s) + UART (+ possibly second UART) + I2C + ... My impression is that if several interrupts are triggered at various times during interrupts disabled (or high priority executing) the one that happened first will be the one executed upon the enable. I base this on the phrase "If two interrupts occur at the same time" which is not "If two interrupts are enabled the same time" I do not right now have hardware to try this but it would be easy to disable interrupts, create EXI1, then EXI0 and see which got executed first. I think this is interesting and will, if someone does not beat me to it, try it when I can. It might even be 'derivative specific'. Erik |
| Topic | Author | Date |
| Timer Problem Assembly Code | 01/01/70 00:00 | |
| Interrupt priorities... | 01/01/70 00:00 | |
| Also... | 01/01/70 00:00 | |
| The missing words | 01/01/70 00:00 | |
| You sure? | 01/01/70 00:00 | |
| many ways to skin a cat | 01/01/70 00:00 | |
| Actually very relevant | 01/01/70 00:00 | |
| My impression is | 01/01/70 00:00 | |
| Interesting, but missing the point surely... | 01/01/70 00:00 | |
| Interrupts are 'saved' | 01/01/70 00:00 | |
| Soft interrupts | 01/01/70 00:00 | |
| in a '51 forum | 01/01/70 00:00 | |
| Still missing the point... | 01/01/70 00:00 | |
| the missing reti's have already been mentioned | 01/01/70 00:00 | |
Apart from missing reti... | 01/01/70 00:00 | |
| Interupt priorities | 01/01/70 00:00 |