| ??? 03/13/10 08:09 Read: times |
#174103 - Digital Delay Lines Responding to: ???'s previous message |
What's really odd about these guys is that the input pulsewidth and output pulsewidth have to be carefully monitored. The longer the digital delay the longer the input pulsewidth has to be. Likewise, the shorter the delay, the shorter your input pulsewidth can be. So one needs to take care as to how much delay they have and how long their digital inputs are allowed to be. And yes, there are already digital delay line ASICs. When I remember the site, I will post it. |
| Topic | Author | Date |
| Counter IC for Ultrasonic flow meter | 01/01/70 00:00 | |
| specialized circuits | 01/01/70 00:00 | |
| FPGA TDC | 01/01/70 00:00 | |
| FPGA difficult | 01/01/70 00:00 | |
| ACAM TDC-GPX ? | 01/01/70 00:00 | |
| Interesting | 01/01/70 00:00 | |
| Mayabe a CPLD would be easier | 01/01/70 00:00 | |
| CPLD | 01/01/70 00:00 | |
| GP2 | 01/01/70 00:00 | |
| I like those GP2 devices | 01/01/70 00:00 | |
Resolution | 01/01/70 00:00 | |
| Not too difficult | 01/01/70 00:00 | |
| psec | 01/01/70 00:00 | |
| there is no reason why not | 01/01/70 00:00 | |
| Silicon delay line | 01/01/70 00:00 | |
| Digital Delay Lines | 01/01/70 00:00 |