| ??? 03/10/10 00:46 Read: times |
#173966 - Mayabe a CPLD would be easier Responding to: ???'s previous message |
Though they're more costly per fliflop, CPLD's are not terribly expensive and if it takes you more than 1 hour to learn how to enter the schematic and compile it, then something's wrong. Low-cost CPLD's operate at rates into the hundreds of MHz, though not terribly many hundreds.
FPGA's aren't difficult either if you use schematics, but there are more steps and more pitfalls. RE |
| Topic | Author | Date |
| Counter IC for Ultrasonic flow meter | 01/01/70 00:00 | |
| specialized circuits | 01/01/70 00:00 | |
| FPGA TDC | 01/01/70 00:00 | |
| FPGA difficult | 01/01/70 00:00 | |
| ACAM TDC-GPX ? | 01/01/70 00:00 | |
| Interesting | 01/01/70 00:00 | |
| Mayabe a CPLD would be easier | 01/01/70 00:00 | |
| CPLD | 01/01/70 00:00 | |
| GP2 | 01/01/70 00:00 | |
| I like those GP2 devices | 01/01/70 00:00 | |
Resolution | 01/01/70 00:00 | |
| Not too difficult | 01/01/70 00:00 | |
| psec | 01/01/70 00:00 | |
| there is no reason why not | 01/01/70 00:00 | |
| Silicon delay line | 01/01/70 00:00 | |
| Digital Delay Lines | 01/01/70 00:00 |