| ??? 03/13/10 03:49 Read: times |
#174099 - Silicon delay line Responding to: ???'s previous message |
FPGA TDC is based on silicon delay line integrated in recent FPGA
Silicon delay line consists of many logic buffers connected in serial. Tiny propagation delay (10s ps) of each buffer gives delay line operation. Each junction of buffers is wired to trigger input of flip-flops, this array of FFs gives "variable" delayed capture of input signal. Primary purpose of delay line is phase alignment of input signal. But the application of delay line extends to digital processing of signals around GHz. Delay line PLL of high-/super-speed USB and PCI express is the fruit of this technology. FPGA TDC also counts in on this line. I don't see any CPLD which mounts delay line yet. Tsuneo |
| Topic | Author | Date |
| Counter IC for Ultrasonic flow meter | 01/01/70 00:00 | |
| specialized circuits | 01/01/70 00:00 | |
| FPGA TDC | 01/01/70 00:00 | |
| FPGA difficult | 01/01/70 00:00 | |
| ACAM TDC-GPX ? | 01/01/70 00:00 | |
| Interesting | 01/01/70 00:00 | |
| Mayabe a CPLD would be easier | 01/01/70 00:00 | |
| CPLD | 01/01/70 00:00 | |
| GP2 | 01/01/70 00:00 | |
| I like those GP2 devices | 01/01/70 00:00 | |
Resolution | 01/01/70 00:00 | |
| Not too difficult | 01/01/70 00:00 | |
| psec | 01/01/70 00:00 | |
| there is no reason why not | 01/01/70 00:00 | |
| Silicon delay line | 01/01/70 00:00 | |
| Digital Delay Lines | 01/01/70 00:00 |