??? 01/15/10 14:00 Read: times |
#172488 - illustration of edge difference? Responding to: ???'s previous message |
This is an illustration, not a discussion of a SILabs chip
if you look at the datasheet for the SILabs f12x/f13x you will see Bit 5: CKPHA: SPI0 Clock Phase. This bit controls the SPI0 clock phase. 0: Data centered on first edge of SCK period.* 1: Data centered on second edge of SCK period.* Bit 4: CKPOL: SPI0 Clock Polarity. This bit controls the SPI0 clock polarity. 0: SCK line low in idle state. 1: SCK line high in idle state. This is an illustration of how varied the SPI can be and as a simulator SIMULATES (with the same satisfaction as simulated sex), you have no idea if your setup match the clock phase and polarity. Erik |