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???
04/30/09 16:51
Modified:
  04/30/09 16:59

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#164967 - yes, but the overlooked fact is ..
Responding to: ???'s previous message
If your initialising routines produce any unsafe states, you have coded them wrong.

yes, but the overlooked fact is .. that reset produce unsafe states, thus you have designed the hardware wrong.

The frequency of Is there a sure shot way of ensuring that the out puts are suppressed at power-on and similar posts show a very sad state of the reading of datasheets before designing.

I have seen designs that relied on "reset is too brief to cause any danger/problem/... when the ports are high" and I have (not in combination) seen power supply noise due to e.g. a cap gone bad resulting in enough noise to almost keep the uC in permanent reset while the rest of the circuitry was not sensitive to the spikes. I wonder when the combination of relying on the briefness of reset and PS noise will do harm.

Erik

List of 11 messages in thread
TopicAuthorDate
Outputs during poweron            01/01/70 00:00      
   Inverted logic            01/01/70 00:00      
      if they were strong enough            01/01/70 00:00      
         depends            01/01/70 00:00      
   You could use an OR-gate...            01/01/70 00:00      
      why not just an inverter?            01/01/70 00:00      
   how about an inverting version?            01/01/70 00:00      
      suggestions            01/01/70 00:00      
         You have keen eyesigt.            01/01/70 00:00      
            yes, but the overlooked fact is ..            01/01/70 00:00      
   3 possibilities            01/01/70 00:00      

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