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???
04/11/09 10:37
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#164534 - Addendum
Responding to: ???'s previous message
Just an addendum - if you think that it is ok to stop the motor in any phase, then the 8 stop states can be empty in the switch statement - either just:
switch (state & 0x0f) {
    case FWD_STOP_S1:
    case FWD_STOP_S2:
    case FWD_STOP_S3:
    case FWD_STOP_S4:
    case BKW_STOP_S1:
    case BKW_STOP_S2:
    case BKW_STOP_S3:
    case BKW_STOP_S4:
        // Nothing to do - just waiting for a running state.
        break;
    case FWD_S1:
    .
    .
}
 
or doing:
switch (state & 0x0f) {
    case FWD_S1:
        .
        .
        break;
    .
    .
    default:
        // Stopped - just wait for a running state.
        ;
}
 
Just make sure that all processed bits of the state variable gets processed or normalized, so that you can't get into an invalid state that locks up your state machine.

List of 40 messages in thread
TopicAuthorDate
how to avoid timer interrupt interrupts serial communication            01/01/70 00:00      
   Here the timing is relevant!            01/01/70 00:00      
   how to avoid timer interrupt interrupts serial communication            01/01/70 00:00      
      reply Kai            01/01/70 00:00      
         Do ms-class delays in any interrupt.            01/01/70 00:00      
            re: Per Westermark            01/01/70 00:00      
               ISR frequency * time significantly below 100%            01/01/70 00:00      
               Not sure, whether I got you...            01/01/70 00:00      
               That is not the main problem            01/01/70 00:00      
                  It's a common mistake...            01/01/70 00:00      
                     oops            01/01/70 00:00      
                        Long ISRs are no problem, unless...            01/01/70 00:00      
          instruction execution cycle/time in C language            01/01/70 00:00      
   ISR is set to 1ms but...            01/01/70 00:00      
      That is the problem            01/01/70 00:00      
         oops            01/01/70 00:00      
            What is the baud rate?            01/01/70 00:00      
               9600 baud            01/01/70 00:00      
                  He has got to be sitting in a interupt            01/01/70 00:00      
                     reply            01/01/70 00:00      
                        Many many more details needed!!            01/01/70 00:00      
                           reply Kai            01/01/70 00:00      
                              Further questions...            01/01/70 00:00      
                                 reply Kai            01/01/70 00:00      
                                    Who tells your micro how the stepper is to be moved?            01/01/70 00:00      
                                       reply            01/01/70 00:00      
                                          So, the stepper is running all the time?            01/01/70 00:00      
                                             ya...this is the purpose of having interrupt            01/01/70 00:00      
                                                Ok, then confirm this please...            01/01/70 00:00      
                                                   reply Kai            01/01/70 00:00      
                                                      Still delays in the ISR?            01/01/70 00:00      
                                                         reply per            01/01/70 00:00      
                                                      I suspect that your ISR is longer than 1msec!            01/01/70 00:00      
                                                         reply            01/01/70 00:00      
                                                         ISR code            01/01/70 00:00      
                                                            Post full ISR            01/01/70 00:00      
                                                               reply            01/01/70 00:00      
                                                                  Still not full ISR shown - and debounce?            01/01/70 00:00      
                                                                     Addendum            01/01/70 00:00      
   T_T            01/01/70 00:00      

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