Hi Oliver,

I'm not familiar with PCIe. How do they control impedance across the edge connectors, and how closely do they match impedance? I'm basing my effort on a paper I read many years ago that reported using grounded vias placed around signal vias to control impedance. The surrounding gnd'd vias supposedly act as sort of orthogonal gnd planes allowing a path for return current.

If you've ever looked at the old parallel connectors (e.g. printer ribbon cables), they used a technique wherein they alternated signal lines next to gnd lines. They said it was for "shielding," but I suspect it was a form of (perhaps fortuitous) impedance control. I'm trying a similar arrangement wherein the entire row of the edge connector contacts are gnd'd. This way, each signal will enter and pass through the connector adjacent to a pseudo-backplane return path.

Rather than just testing to see if it works, I want to measure the realized impedance. I also want to look at the effect of the stubs left by the thru-hole pins. Finally, since I can't really vary the impedance of this geometry (beyond possibly playing with the stub length of the pins), if I can measure it I might be able to adjust the traces to match the impedance, or at least get them close enough to work.

Joe