| ??? 05/26/11 13:37 Modified: 05/26/11 13:47 Read: times |
#182411 - it's been a while Responding to: ???'s previous message |
Is it really bad to have a cap on /RST when the device has an internal VDD monitor that can drive /RST low?
it's been a while so I do not remeber anything except there were documented cases where removing the capacitor eliminated flash loss. Anyone interested is welcome to search the SILabs forum. One possible reason would be an interaction with the "supply reset timeout" black box. if that has any resistance you will end up with a RC slope on the reset. Erik |
| Topic | Author | Date |
| For those of you who like your 8051 in garish colours... | 01/01/70 00:00 | |
| Look away Erik ... | 01/01/70 00:00 | |
| the result of copying | 01/01/70 00:00 | |
| Is it really bad? | 01/01/70 00:00 | |
| it's been a while | 01/01/70 00:00 | |
The cap renders the supply monitor ineffective! | 01/01/70 00:00 |