Note that timed delays means you don't need any sequence of rising and falling edges unless someone sends in input data that needs to be processed. And in that case, the input data is the source of handshake signals through the delay lines.

It is easy to see that a processor or huge logic circuit do not need a central, synchronized clock to operate. But having such a clock has many advantages, while at the same time having the big disadvantage that at high clock frequencies it is very hard to introduce that clock signal into a huge logic circuit without the clock having significant delays between different parts of the circuit. Another disadvantage with a fixed, common, clock is that no part of the chip may run faster than the slowest part. And when that slowest part gets too much in the way, you need to break it into multiple steps so that you can instead run these sub-steps synchronously with the clock. That is the reason why modern processors have pipelines - and instead get stall costs whenever the pipeline have to be refilled after a branch. An asynchronous design will only be slowed by a slow submodule when the signal needs to pass through that module. When the signal path only runs through fast submodules, the asynchronous design can speed up and run much faster than a traditionally clocked design.