Because the 8051 microcontroller, like the overwhelming vast majority of digital designs, uses what's called synchronous logic. On every tick of the clock, each flip-flop in the design looks at its input and drives same to its output. Simultaneously, all of the flip-flop outputs go through some combinatorial logic (AND, OR, NOT, etc gates) to another flip-flip input. The idea is that the outputs of all of the flip-flops have to propagate through all of the combinatorial logic and the results of that logic must be settled at the input of the receiver flop before the next tick of the clock.

You do what's called Static Timing Analysis on the design to determine if all of the logic paths in the design meet the specified clock frequency. STA is a bounded problem since the number of paths in a design is finite. It's easy for a computer to calculate all of the worst-case path delays and report them to you.

Others in this thread have mentioned asynchronous (clockless) logic, which has been a topic for academic research for decades but for various Real Good Reasons, the number of successful commercial devices built with async logic remains insignificant compared to those built with synchronous logic design.

-a