I wish synthesis tools had an option to generate grey-code counters for just this application! They can generate grey code for state machine state registers, but not for general-use incrementing counters.

OK, so waaay off topic here regarding counters: I have some state machines that have the counter embedded. In other words, there might be one state that initializes the counter to zero, or perhaps loads it, and in another state (or states) the counter is incremented or decremented. I noticed that a particular design wasn't meeting timing (240 MHz!) and as such I looked at what the synthesizer was doing.

This is easy to do, no need to look at the generated RTL schematic. The synth report for each entity lists the stuff it works out. So for my counters, I noticed that the tool was generating adders instead of counters, and general-purpose adders are of course slower than counters (no need to deal with two inputs, etc etc).

The solution, then, is to code the counter in the usual way, with only a sync reset and/or load and a count enable, and a modulo to handle rollover if that situation is legal for the design. This synthesizes a counter and things are faster. The state machine needs to assert the counter load enable/clear and count enable when required. Of course this means being cognizant of pipeline delays -- the state machine asserts the counter enable, which is recognized by the counter on the next clock, and thus the new counter output is available on the second clock after the assertion of the enable.

(Of course you could be suicidal and do a two-process state machine so that the counter enable is recognized immediately and you can save a clock, but that leads to a load of issues.)

-a

-a