I am going to guess that the FIFO implementation that you did was in an FPGA. (Where else is one going to have access to the addressing for the FIFO addresses - as of some time back we passed the days of implementing at the package level with gates, FFs and counters).

Did you implement the counter itself as a Gray code counter?

More than likely you did a binary counter followed by the XOR stage to convert the address to Gray code before presenting that to the SRAM. The biggest benefit I am aware of in addressing RAM with Gray code is that the decoder can be fastest if just one bit in the address decoder is changing. If this is true then what you are saying is that the time delay expense through the extra XOR stage is less time than the address decoding delay and settling time due to single bit change savings. Is this a true analysis?

How wide of address field were you working with?

In the analysis is there a address width where narrower width sees no benefit from Gray drive as opposed to binary drive?

Michael Karas