In the classic 8051 application, a transparent latch, controlled by ALE, is used to capture the lower 8 bits of an address driven out Port 0. Recall that during external memory access, Port 0 is multiplexed between the 8 address LSbs and the 8 data bits, and ALE is used to demux.

When the latch enable is high, the input flows through to the output. The allows for all 16 bits of the address to be made available immediately for decode. (Or, in the 8-bit address case, the whole address is made available.) You get a head start preparing for read access.

After the 8051 does the address phase of the cycle, ALE is brought low. This captures whatever is driving the latch's D input. The output is whatever was latched. The inputs can change in any manner but the output is not affected. And of course for 8051, Port 0 is now the 8-bit data port and can be driven either by the 8051 (for a write) or by external logic/memory (for a read).

If you were to change the transparent latch to a flip-flop, things get tricky. If the flip-flop is rising-edge triggered (like the 74xx574) then the register stores the Port 0 contents as soon as ALE is asserted. And if you read the 8051 "bible," you will see that the address bits driven out Port 0 aren't valid on the rising edge of ALE! If the register was sensitive to the falling edge of its clock (and I can't find anything in the TI or NXP catalog that is), then the slave device won't see the full address until the end of ALE time, which reduces the address available time on reads.

I think this covers all of the bases.

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