They're given to comments such as "2+3 often is thought to equal 5, but it has been pointed out that it sometimes is not."

A latch often is an and-or gate with feedback. It is a combinatorial construct that responds to levels. Improperly constructed, it can have ambiguities and/or glitches.

A flipflop is an edge-triggered construct that responds to either positive or transitions on its clock input but generally not both. Improperly applied, it can become metastabile for a considerable time, sometimes longer than the clock period.

There are probably better ways of describing these two different constructs.

If you are considering using a clocked (e.g. 74HC574) register in place of the level-gated (74HC573) latch you had best know exactly when and how to clock the register. It always depends on the application. Flipflops generally demand considerable data setup time before the clock. Latches generally require considerable data hold time after the gate pulse ends. Clearly they are not always suitable for the same task.

RE