I've had to build a few that were "nearly" complete logic analyzers, but needed complex triggering logic. If you use the on-chip memory, of which there's not very much, as a trigger FIFO, and use external memory to buffer the samples, I think you'll have a better set of triggering options, like wait until THIS happens nnn times, then wait for THAT to occur, then wait for This_Other_Thing mmm times, ... you get the picture. It's not nearly as hard as one might think.

The PC software IS the crux.

RE