| ??? 11/29/06 04:43 Modified: 11/29/06 04:44 Read: times |
#128645 - To... Responding to: ???'s previous message |
Ralph said:
Why would an engineer tie pins 3,4,14,15,16,17,18 & 19 all together????? To enhance the fan-out capability. To increase the sink and source currents. To diminish internal voltage drops (e.g. saturation voltages), which make the output signal to differ from supply rails. Kai |
| Topic | Author | Date |
| Unknown pinouts application | 01/01/70 00:00 | |
| who can tell | 01/01/70 00:00 | |
| i did wonder why the ports were paralleled | 01/01/70 00:00 | |
| Serial Converter | 01/01/70 00:00 | |
| more information | 01/01/70 00:00 | |
| To... | 01/01/70 00:00 | |
| Yes but | 01/01/70 00:00 | |
| Hmm... | 01/01/70 00:00 | |
| What tells the scope? | 01/01/70 00:00 | |
| Nothing | 01/01/70 00:00 | |
| Level? | 01/01/70 00:00 | |
| What will happen | 01/01/70 00:00 | |
| Improper load? | 01/01/70 00:00 | |
| Jez see this | 01/01/70 00:00 | |
| Hhm, but this paralleling is widely used! | 01/01/70 00:00 | |
| Parallel MOS transistors are fine | 01/01/70 00:00 | |
| Perfectly safe? | 01/01/70 00:00 | |
| Reasonably safe | 01/01/70 00:00 | |
| What is this circuit intended to do, Ralph? | 01/01/70 00:00 | |
| What's it to do | 01/01/70 00:00 | |
What it does | 01/01/70 00:00 | |
| Just out of interest lynn, | 01/01/70 00:00 | |
| FPGA conversion cost | 01/01/70 00:00 |