Paralleling of transistors in this way is widely used, though!
Don't forget, that Uce(sat) is not constant, but depends on actual collector emitter current, in a way, that Uce(sat) increases with increasing collector emitter current. This tendency prevents, that only one transistor will carry the whole current and makes, that the current more or else evenly distributes over the paralleled transistors.

If all these transistors are not sitting on the same die, it can be helpful sometimes, to enhance this distributing by artificially increasing the collector emitter path resistance of each transistor, by simply inserting a small resistance at each collector before feeding them together. This, to manage manufacturing tolerances.

The same is true for NPN, PNP, NMOS and PMOS transistors.

Kai