First of all, while I know setup and hold times are very relevant, they're not the thing that bothers me about this particular spec.

However, just to be contrary, I have to say that a '373/573 has on clock, being a "transparent latch" which passes data from its input to its output when the gate is, in this case, high, and holds the data on its outputs when the gate goes low. A 'D' flipflop, e.g. 74374, or 7474, is a clocked flipflop which has essentially two stages, an input latch and an output latch, the input latch being set or cleared by the data during clock low, and the output from that stage being transferred to the output stage when the clock goes high. Since the input of the ouput stage doesn't change when the clock is low, and the output stage doesnt change when the clock is high, it transitions only on the positive-going edge of the clock. Aside from technological limitations of prop-delay through the output stage, there is little restriction on the clock pulse width. As a result, the 'D' flipflop has a setup time requirement, but little if any hold time requirement.

OTOH, the transparent latch is a single latch consisting of a combinatorial loop. It has essentially no setup time requirement, but requires enough hold time on the input data after the gate switches from active to inactive, so that the data state at the time of transition can still propagate through the latch.

This latter fact is the reason the absence of a minimum pulse width but the specification of a maximum and typical for the pulse width of the gate active state is senseless.

A minimum would make sense for either a latch or a flipflop, since the active (high) state must be long enough to meet minimal requirements in either case. For the 'D' register, it must be long enough to prevent the input stage from changing state while the data propagates through the output stage, and also be long enough to allow for that propagation to occur. In the case of the latch, it must be long enough to allow for the data valid at the time it goes active to propagate to the output and back to the input before it goes low, else the combinatorial loop will fail.

This latter assertion is what makes the setup and hold times so important.

The gate, however behaves not at all like a clock. Input data flows through the latch as though it were a buffer so long as it is active and propagates through the latch so long as the gate is active, no matter how long. Since it relies on feedback, the data on the input must have time to propagate to the output and back to the input logic if it is what is to be preserved when the gate goes inactive (low). Beyond that minimum, there is no limit on how wide the gate pulse can be.

The clock rising edge on a positive-clocked element ENDS the period during which input data is sampled, at the input latch, and enables it to propagate through the output latch. Since the clocked flipflop doesn't depend on feedback, no hold time is necessary. This setup time must be long enough to operate the input latch, which holds its input data once the clock goes high. The output latch then propagates the data so long as the clock is high, and then continues to do so after it goes low again, irrespective of what happens on the input stage.

RE