| ??? 11/08/11 16:00 Read: times |
#184588 - Impedance With Divider Responding to: ???'s previous message |
If you must use a resistor divider to scale the signal then in this case you want to get the source impedance as low as possible and the ADC/MUX load impedance as high as possible. Then hope that the parallel resistance of the two resistors in the divider is greater than 10->100X the source impedance and that the ADC/MUX impedance is greater than 10->100X the parallel divider resistance. The 10-100X factors are seat of the pants guidelines for simpler applications where the utmost in precision is not needed.
If it is not possible to come close to the above then the solution is to insert an OPAMP stage to provide the scaling and present a low impedance source to the ADC/MUX component. Michael Karas |
| Topic | Author | Date |
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| SPI | 01/01/70 00:00 | |
| gotcha | 01/01/70 00:00 | |
| 3.4 MHz I2C | 01/01/70 00:00 | |
| RE: SPI is simpler | 01/01/70 00:00 | |
| One other quick question for all you smart people. | 01/01/70 00:00 | |
| Some things to consider.... | 01/01/70 00:00 | |
| Full range and clipping | 01/01/70 00:00 | |
| Impedance | 01/01/70 00:00 | |
| You sure? | 01/01/70 00:00 | |
| Impedance With Divider | 01/01/70 00:00 | |
Impedance matching | 01/01/70 00:00 | |
| if I recall | 01/01/70 00:00 |