| ??? 08/24/11 13:43 Read: times |
#183458 - I meant port pins Responding to: ???'s previous message |
Michael Karas said:
Maarten Brock said:
When you disable a high priority peripheral the lower peripherals with lower priority shift down to lower pin numbers. Or when you enable one they shift up. The shifting that occurs is along the order of assignments for the crossbar for any particular part family. Disabling the high priority peripheral does not necessarily move the lower priority peripherals to lower pin numbers. In fact for a C8051F340 family part they would move to higher pin numbers! Same appears to be true for the C8051F120 part. I think I was right, but maybe I should have said port pin instead of pin number. On the F120 (but also the F340) I consider the SPI peripheral to have a higher priority than UART1. I also consider P0.0 the lowest port pin and P3.7 the highest. I was not thinking in real pin numbers on the package as that mapping can be quite irregular. If only UART0, SPI0 and UART1 are enabled they get mapped to P0.0-1, P0.2-5, P0.6-7 respectively. If the SPI0 is disabled UART1 shifts to P0.2-3. But as said, play with the Config Wizard and you will quickly get the hang of it. I think it's clear that SiLabs also found out that the crossbar is powerful yet intolerant to changes and therefor added the SKIP registers in later devices. Unfortunately the F120 does not have them. I consider the crossbar with skip powerful enough for my needs and certainly more powerful than 2 alternatives per signal configurations. Maarten |
| Topic | Author | Date |
| C8051F120 SPI0 and UART1 | 01/01/70 00:00 | |
| priority crossbar | 01/01/70 00:00 | |
| Caution on Using SiLabs Parts | 01/01/70 00:00 | |
| Hurtful choice | 01/01/70 00:00 | |
| the story | 01/01/70 00:00 | |
| Best is normally in the middle | 01/01/70 00:00 | |
| TY | 01/01/70 00:00 | |
| I meant port pins | 01/01/70 00:00 | |
The Skip Registers | 01/01/70 00:00 |